Semiconductor Packaging

Peter has authored 20 new patents in this arena. Some relate to new cooling methods, and others to new methods of testing and rework. The central thrust is achieving low cost through miniaturization. This is primarily achieved through wafer and panel-level processing, and stacking chips vertically, with or without the use of through-silicon-vias (TSVs). The issues of structure, cooling, testing, and rework are simultaneously addressed to create a system-level solution.

Interconnections

We think that conventional printed circuit boards (PCBs) will be around for a long time as motherboards. However, they do not support dense circuit configurations of the new generation; they are being replaced by fine-trace circuits created using build-up layers on thin film substrates. The fine-trace technology is becoming more available and the costs are decreasing. In addition, it has become practical to use copper cores, and this can lead to substantial performance advantages at the system or module level.

 

 

 

 

 

 

 

 

 

Figure 1, integrated assembly using buckled pillars

Figure 1 shows an optional solder free assembly with a heterogeneous mix of semiconductor components. Commercial stud bumping machines can be adapted to provide pillars of any length. Also an automated procedure can provide pillars of different lengths for an entire layer. For an animation of the patented buckled pillar process, see a recent web article published in "Advanced Packaging", buckled pillar animation.

For fragile die, the ultrasonic action of the bonder in the vicinity of active devices may be problematic; in this case the pillars will preferably be gold pillars, and the configuration will be rearranged so that the ultrasonic action occurs at the substrate instead of at the die.

For further details, see for example the following patents:

7,427,809 Issued Repairable Three-dimensional Semiconductor Subsystem

This patent is directed at tightly packed semiconductor systems that can be tested and repaired at various stages in the system integration process. The flip chip connectors include spring elements that may be produced in a wafer level process employing copper plated pillars for example. The female side of each flip chip connector may include a well, and the well may be formed using a programmable laser in an automated method not requiring a mask (use the Contact Us link to obtain more details). In addition to the preferred embodiment of electro-formed pillars, the claim language also includes "bump or wire like terminals", and these may be implemented using stud bumping equipment as described above. This patent is broad in scope, covering semiconductor elements as integration platforms, through wafer connections (also known as through-silicon vias or TSVs), and integration of heterogeneous elements such as high performance flex cables. Passive devices may be included. Claim 11 combines the flip chip structure with a novel heat sinking method employing flexible copper fingers in an interface adaptor. The conductive fluid in the well may be implemented using modern variants such as a conductive fluid comprising carbon nanotubes in a liquid base. This can result in very low contact forces, suitable for assemblies having a large number of input/output connections. Compared with conventional pogo spring elements requiring approximately 10 grams of force per pin, the required force may be less than a milligram. This implies that a million probe points can be implemented with a total wafer force of 1 kilogram. The conductive fluid in the wells may be adapted such that following system level test it can be hardened to form a solid (see Claim 3). Accordingly, this patent enables a broad range of advanced semiconductor assemblies, including the type shown in Figure 1, but also including generalized semiconductor systems that incorporate bare die or other semiconductor elements in highly compact arrangements.

 

7,408,258 Issued Interconnection Circuit and Electronic Module Utilizing Same

 

 

 

 

 

 

 

 

Figure 2. Rugged module employing copper substrate and cover layer, having built-in electromagnetic screening.

This patent broadly claims the use of copper substrates for boards and modules. Fabricators have recently become more widely available for creating high density interconnection (HDI) circuits on copper cores. The claims cover integration of IC chips, cables, radio transceivers, and generalized electronic components. They also cover the use of copper layers to create advanced cooling structures, and also hermetic structures where desirable. The cooling structures may include an adaptation for circulating a cooling fluid. Copper has been an under-appreciated substrate material and offers the following advantages:

• Excellent thermal conductivity
• Built-in electromagnetic screening
• Impermeability to water
• Available at low cost
• Thermal expansion matched with glass epoxy substrates such as FR4

Flip chip connectors having good mechanical compliance and excellent rework capabilities may be employed for attaching the electronic components. Stud bumps may be used as chip terminals, and corresponding conductive wells may be used to accept the stud bumps.

 

7,254,024 Issued Cooling Apparatus and Method

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Definition of a Microblade

 

 

 

 

 

 

 

 

Figure 4. Cooling tank containing an array of microblades.

This patent covers a thermal architecture for an electronic system consisting of electronic modules called microblades. It is the first patent to include the notion of hermetic modules in a cooling tank; consequently the claims are broad. The microblades are arrayed in the cooling tank. Each microblade is an electronic assembly contained within a sealed copper sheath. It is rugged and hermetic except at the top where a cable exits through potting material. The flat cable may employ transmission line structures for high performance. The cooling method is well suited to data centers, enabling a maximum junction temperature of around 20 degrees Centigrade for example. Such low temperature operation may be used to create either higher performance or lower power at the system level.

 

7,163,830 Issued Method for Temporarily Engaging Electronic Component for Test

 

 

 

 

 

 

 

 

 

 

Figure 5. Novel chip socket employs fluid filled wells

This patent is co-authored with Dr. Howard Johnson, a world authority on digital design and signal integrity. It builds on recent advances in copper pillar technology, mating the pillars with corresponding wells, each well filled with a conductive fluid. This combination provides a temporary connection for testing; the testing can be at full speed and full power. If a chip proves defective during test, it can be easily replaced. Once the system is fully functional, the conductive fluid or paste can be hardened to form a permanent connection.

 

7,586,747 Issued Scalable Subsystem Architecture having Integrated Cooling Channels

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6. Example of a scalable subsystem with integrated cooling channels..

This patent is directed at scalable subsystems employing BGA interconnections between stacked layers. By using copper-cored interconnection substrates, cooling channels can be provided in the stack where necessary for aggressive cooling. Chilled water can be provided in the cooling channels for example. The cooling channel layers also provide a convenient place in the stack where rework can be accomplished, to replace a defective layer.

 

Semiconductor wafer tester

 

 

 

 

 

Figure 7. Semiconductor wafer tester

The figure above shows a wafer tester design for high powered microprocessor chips. This apparatus and method have the potential to revolutionize testing of high-powered wafers. A conventional probe card is not used. Rather, pillar-in-well connections are made between the product wafer and the test wafer, and also for attaching test chips to the stimulus wafer. 350,000 simultaneous probe points can be accommodated on the product wafer, with a normal force of less than 1 kilogram on the wafer. Finally, because of the tight packaging and the short leads, the complete set of microprocessors on the product wafer can be operated simultaneously at full speed.

Water is flowed over the back side of the product wafer to achieve aggressive cooling. At a flow rate of five liters per minute, 20,000 watts of heat can be extracted, enough to accommodate the highest powered microprocessor designs of today.

See the following published patent for more details:

20070007983 Published Semiconductor Wafer Tester

Novel low-k dielectric material

 

 

 

 

 

 

 

 

Figure 8. Gridded dielectric construction.

A method is described for fabricating a dual-component dielectric layer having a relative dielectric constant of approximately 2.1. In return for an extra processing step the best materials can be used and problems relating to thermal mismatch, adhesion, delamination, or bowing can be overcome. With judicious selection of the two materials, patterning of the dielectric layer either by an imprinting method or by a photo process can be transparent to the presence of the dual dielectric. See the following published patent for further details.

7,535,107 Issued Tiled Construction of Layered Materials

High-speed BGA socket

 

 

 

 

 

 

 

 

Figure 9. Several views of low-profile BGA socket.

The above figure illustrates a new type of high speed socket for BGA-packaged devices. The BGA interface is currently the most popular interface for packaged devices. For expensive chips like microprocessors, it is economic not to add them to a circuit board until the last minute before shipping. However, the socket must be capable of high speed, supporting signaling rates such as 1Gbps, and preferably will have a small footprint on the board.

This socket construction is further described in a provisional patent entitled Interposer Apparatus and Method. Prior to publication, this patent can be made available under a non-disclosure agreement. A related patent that has issued is:

7,163,830 Issued Method for Temporarily Engaging Electronic Component for Test

Both are assigned to Salmon Technologies, LLC and are available for co-development with a partner, or for sale or license.