Publications

March 2010

Fuze Electronics Miniaturization

This paper explores a new architecture for fuze electronics modules that must withstand G-forces in excess of 100,000 G's.
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September 2009

Magnavox and Intel: An Oddysey

Co-authored with Stan Mazor, IEEE Annals of the History of Computing, September, 2009. This article presents the story of the 8244 video game chip developed by Intel for Magnavox. Peter Salmon was the lead chip designer.
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June 2009

Patent Landscape Analysis: Servers and Data Centers

This paper explores the patent landscape and dominant corporate players in the arena of servers and data centers. It reveals that critical new technology areas are not well covered in the existing patent literature. Read more...

December 2008

Solder Free Connectors Using Buckled Pillars

The MEPTEC Report, December 2008. This paper includes a discussion about replacing BGA packaged devices, the buckled pillar solution, a new cost trade-off, a solder-free implementation, and the versatility of stud bumping. Read more...

December 2008

3D Silicon Integration: A Novel Approach for Immediate Implementation

Unpublished white paper, December 2008. This paper describes a new approach to packaging high-power systems like servers and routers. Water cooling is used and a thermal model is provided. Through silicon vias (TSVs) can be accommodated, but are not required to produce effective stacking configurations. Read more...

November 2008

Solid State Printing: A New High-Speed Printing Technology

Published in the Hard Copy Observer by Lyra Research, Nov-Dec 2008. This article describes a digital printing press design that leverages the computational and multi-channel drive capability of integrated circuits to create a digital press having potentially better performance than the best digital presses currently available. Read more...

September 2008

Solder Free Connectors Using Buckled Pillars (with animation)

Advanced Packaging, published on-line, September 2008. The article includes an animation of the manufacturing sequence for buckled pillar connectors. The connectors are useful for creating solder-free assemblies, particularly for high-power electronics. Read more...

May 14, 2008

System Integration Method: Next Generation Packaging for Servers and Supercomputers

IEEE CPMT dinner meeting, Sunnyvale, California, May 14, 2008. This PowerPoint presentation uses a recently announced IBM water cooling concept for comparison with a proposed new water cooling method. Read more...

February 28, 2008

High Performance Modules on Copper Substrates

Meptec's 4th annual conference: The Heat is On, Sunnyvale, California, February 28, 2008. This PowerPoint presentation highlights the many virtues of copper: it is available and inexpensive; it provides good mechanical support; it is an excellent thermal and electrical conductor; it is impervious to water; and it can be manufactured as a panel or as a wafer. Read more...

November 1-3, 2006

Copper Panel Fabrication and Stacking Concept for VLP FB DIMMs

3rd International Wafer Level Packaging Conference, San Jose, California, Nov. 1-3, 2006. This PowerPoint presentation examines feasibility questions regarding the possibility of creating a 16 Gbyte DIMM using an 8-high stack of 1Gbit chips. Read more...

September 10-13, 2006

Copper Pillar Well Methodology and Implementation in a VLP FB DIMM

2006 KGD Packaging and Test Workshop, Napa California, Sept. 10-13, 2006. This PowerPoint presentation examines the possibility of building a very low profile fully buffered dual inline memory module using copper-pillar-well connectors and copper-cored substrates. It also suggests that the packaging technology may find a place in non-memory products. Read more...

April 18, 2006

The World Through the Eyes of an Inventor

PowerPoint presentation. IEEE CNSV dinner meeting, Sunnyvale, California, April 18, 2006. The musing of an inventor is presented, including comments about the SBIR process, electrostatic motors, patents, and the creative process. Read more...

November 3-4, 2005

Repairable 3D Semiconductor Subsystem*

2nd International Wafer Level Packaging Conference, San Jose, California, Nov. 3-4, 2005. This paper aggressively examines what could potentially be achieved with re-workable flip chip connectors and high performance copper-cored substrates. Read more...

* This paper won the Best in Conference Award

October 10-12, 2004

Novel SIP Design Concept: Stacked Copper BGA

1st International Wafer Level Packaging Conference, San Jose, California, Oct. 10-12, 2004. This PowerPoint presentation examines creative concepts for solving power problems projected by the International Technology Roadmap for Semiconductors (ITRS). Read more...

February 24-26, 2004

Flip Chip Connections Using Bumps, Wells, and Imprinting

IPC Printed Circuits Expo, Apex, and the Designers' Summit, Anaheim, California, Feb. 24-26, 2004. This paper examines concepts for new flip chip connectors, and the use of imprinting to build high density interconnection (HDI) circuits. Testing and re-work strategies are also discussed. Read more...

March 24-27, 2003

Advanced System Packaging

4th International Symposium on Quality Electronic Design, IEEE, San Jose, California, Mar. 24-27, 2003. This PowerPoint presentaton explores the possibility of using mature glass fabrication methods developed for flat panel displays (FPDs) for the fabrication of general-purpose electronic systems. Read more...

January 27-29, 2003

Chip on Flex with 5-Micron Features

Proceedings of SPIE, Micromachining and Microfabrication Process Technology VIII, San Jose, California, Jan. 27-29, 2003. This paper explores the possibility of creating fine-featured circuits on polyimide substrates using the mature glass fabrication methods developed for flat panel displays (FPDs). Read more...